Many packages are known which contain plural semiconductor die such as two power MOSFETs, or other switching or MOSgated devices (MOSFETs, IGBTs, thyristors, and the like) or a power MOSgated device die and a control circuit die for the power MOSFET die. Such packages can define series or parallel connected die or a “smart” power semiconductor in which a power device is controlled by an integrated circuit die. These die are generally laid out side by side and are laterally spaced atop a lead frame, or other support surface and are connected through the lead frame and/or by wire bonds to their upper surfaces. Other geometries are known in which one chip is fixed to the top of another chip, with the chips interconnected by laterally displaced wire bonds to a lead frame.
These arrangements of die take up lateral space or area and a relatively large “footprint” or area is required on the support substrate to support the die.
In applications, in which space is at a premium, as in portable electronic devices, it would be desirable to provide a package structure which could have the same effective active area of silicon for the power die and control die but which has a reduced footprint on the support such as a printed circuit board.